As semiconductor devices have become more highly integrated, fabrication of devices having a high speed has become more desirable. In order to lower resistance of structures such as gate electrodes and source/drain contacts in devices such as static random access memories (SRAMs) and logic devices, materials having low resistivity, e.g., suicides compounds of metal and silicon, have been widely used.
FIGS. 1A through 1D are sectional views which illustrate a conventional self-aligned silicide (silicide) process. Referring to FIG. 1A, a gate insulating film 4 and a polysilicon gate electrode 6 are formed in an active region of a semiconductor substrate 2. An insulating layer is then deposited on the resultant structure and anisotropically etched to form spacers 8 on the sidewalls of the gate electrode 6. Using the spacers 8 and the gate electrode 6 as an ion-implantation mask, impurities are then implanted into the semiconductor substrate 2 to thereby form a source/drain region 10.
Referring to FIGS. 1B and 1C, a refractory metal layer 12, e.g., a titanium (Ti) or cobalt (Co) layer, is deposited and heat treated to thereby form silicide regions 12a, 12b, the silicide being a heat-treated compound of silicon and the refractory metal, such as titanium silicide (TiSi.sub.2) or cobalt silicide (CoSi.sub.2). As illustrated, the silicide regions 12a, 12b are formed where the refractory metal layer 12 contacts silicon, i.e., on the source/drain regions 10 and the gate electrode 6. The unreacted refractory metal may subsequently be removed, thus allowing the silicide regions 12a, 12b to be formed without an additional photolithography process. The silicide region 12a on the gate electrode 6 can reduce the sheet resistance of the gate electrode 6 and the silicide region 12b formed on the surface of the source/drain region 10 can reduce contact resistance between the source/drain region 10 and an interconnection region. Referring to FIG. 1D, a planarized interlayer dielectric film 14 may subsequently be formed on the resultant structure of FIG. 1C, and a photolithography process performed to form contact holes for connecting the gate electrode 6 and the source/drain regions 10 to subsequently formed regions.
However, if subsequent processing involves heat treatment, problems may arise. As shown in FIG. 2, agglomeration or encroachment of silicide may occur at a contact portion of the source/drain 10 and a barrier layer 16 (or an interconnection region 18, if the barrier layer 16 is not present), thereby attacking an interface A between the source/drain region 10 and the substrate 2. This may cause excessive junction leakage current, increasing power consumption of a device and deteriorating its reliability. Moreover, the silicide regions usually absorb a great deal of impurities, especially boron, from the substrate during formation and during subsequent heat treatment. Consequently, at an interface between an interconnection region and a source/drain region doped with a P-type impurity such as boron, the concentration of boron at the interface between the source/drain region and the interconnection region may be decreased due to absorption by the silicide, thus increasing contact resistance between the source/drain region and the interconnection region. The increase in the contact resistance can deteriorate the speed of the device.